1. Field of Invention
This invention relates generally to radio frequency (RF) power oscillators for contactless card antennas, and more specifically to an RF power oscillator utilizing tapped delay lines and digital buffers for shaping the operating frequency input signal to minimize unwanted harmonics and reduce electromagnetic interference.
2. Background
Smart card signal transmission circuitry includes at least one oscillator circuit for generating a modulated carrier signal for transmission of data to a smart card. A common class of output stage utilized for RF communication is Class-A output stages which is capable of generating pure sine waves due to its linear characteristics. Due to the low efficiency of the Class-A output stages, non-linear power stages or square wave generators are typically used in the prior art as the radio frequency (RF) power oscillators for contactless card antennas. However, these non-linear or square wave generators present several disadvantages for use in providing a modulated carrier signal for transmission by smart card antennas.
A disadvantage of the prior art nonlinear transistor stage is the dependency on the transistors gain parameters. This type of output stage is typically based on a NPN transistor with a parallel LC resonance circuit as collector load. This circuit is capable of generating fairly pure sine waves, but the nonlinear nature of the circuit makes it very hard to control the amplitude of the output signal and especially the modulation index in case amplitude modulation is desired.
A disadvantage of the prior art square wave generator is that the generator draws a large current spike from the power supply when it switches state due to the charging and discharging of inherent capacitances in the switching circuit. The current spike typically has a duration comparable to the rise and fall-time of the output square wave, resulting in a current spike with a very broad electromagnetic interference (EMI) noise spectrum. The prior art circuits that use the nonlinear or square wave generator also require the use of a low pass or a band pass filter before the modulated signals are fed to the tuned antenna coil to rid the signal of the harmonics of the operating frequency. However, these filters include combinations of capacitors and inductors which produce additional signal interference between the filter and the tuned antenna coil resulting in unwanted resonances at frequencies outside the operating frequency of the smart card communication system.
Therefore, a need continues to exist for a radio frequency power oscillator for use with contactless smart card antennas that will produce a high current, modulated signal with an improved wave shape and accurately controlled amplitude without drawing excessive current spikes and with reduced electromagnetic interference.
It is an advantage of the present invention to provide a power oscillator circuit for control of the wave-shape and the amplitude of an output data signal.
It is another advantage to provide a high current/low impedance modulated output signal for use with a smart card antenna.
Still another advantage is to provide an RF power circuit having low electromagnetic interference.
It is yet another advantage that the amplitude and modulation index is accurately controlled by the supply voltage of the output stage.
In the exemplary embodiment of the present invention a power oscillator circuit generates a wave-shaped and amplitude controlled output signal for transmission on a smart card antenna. The power oscillator includes an on/off modulated carrier input signal connected to a tapped delay line. Multiple tap outputs of the delay line are connected to the inputs of a selected number of buffers. The outputs of the buffers are connected in series with same value resistors, and the buffer output resistor lines are connected in parallel to a single node. The progressively delayed input signals on the buffer output resistor lines are hard-wire combined at the single node to produce a wave-shaped output signal. For a square wave carrier input signal having a 50% duty cycle, and a tapped delay line have equal-length delay taps, the resulting wave-shaped output signal is trapezoidal with a rise and fall time equal to the number of taps multiplied by the delay time between taps. In other embodiments of the invention, the power oscillator may be configured to generate a different output signal depending upon the configurations of delay taps used. Since the buffer drivers for each delayed output signal switch state at slightly different times, the amplitude and bandwidth of emitted electromagnetic interference (EMI) is reduced significantly.
The power oscillator of the present invention also offers the advantage of control of the amplitude of the wave-shaped output signal for amplitude modulation of less than 100%. The exemplary embodiment provides 0-25% modulation utilizing a power supply circuit which outputs a desired transmission voltage. These modulation percentages are used in the particular applications for smart card antennas as specified in the ISO14443 standard. As an example, an ISO14443 type-B contactless smart card requires a modulation index of 10%. This is achieved in the present invention by switching between a supply voltage of Vmean+10% and Vmeanxe2x88x9210%. If Vmean+10% is 5.0V, then Vmean equals 5V1.10, and Vmeanxe2x88x9210% equals 0.90xc3x97(5V/1.10), or 4.09V. The transmission voltage generated by the power supply circuit is connected to the power supply inputs of the buffers. The buffers output signals are then limited to the voltage amplitude of the power input to the buffers resulting in the desired 10% modulation index amplitude modulation. The maximum modulation index is limited by the minimum operating voltage of the buffers.
In an exemplary method of the present invention for controlling the wave shape and amplitude of a modulated carrier signal, the modulated carrier signal is produced utilizing a power oscillator circuit which includes readily available, low cost CMOS line drivers as the RF power source. Each line driver is a 74AC541 driver manufactured by Texas Instruments, or any other suitable line driver, which has eight individual buffers. The exemplary embodiment utilizes a total of three line drivers. Two of the buffers of the first line driver are used for driving the delay line, and two of buffers of the third line driver are used for driving the termination of the delay line to either 2.5 v or 0.0 v to conserve energy in idle mode. Therefore, there are twenty buffers available for connection to the twenty taps of the tapped delay line. A square wave signal at the operating frequency and with 50% duty cycle drives the inputs of the CMOS line drivers. If 100% AM modulation is required, the data signal input will be gated digitally, preferably synchronized to the operating frequency. If 0 to 25% modulation is required, the supply voltage for the CMOS line drivers is modulated accordingly by the power supply circuit. The outputs of the CMOS line drivers are connected in parallel with a 82 ohm resistor in series with the output of the CMOS line drivers. This value is chosen in order to minimize the influence of variations in buffer output impedance. If the typical output impedance of the buffer is 25 ohm with a tolerance of +/xe2x88x9250%, then the apparent output impedance tolerance of each buffer will be reduced to +/-12% if 82 ohm 1% resistors are added to the output. The value of the resistors for other embodiments may range from 22 ohms to 100 ohms in accordance with the typical output impedance of the buffers.
The inputs of the CMOS line drivers are connected to the tapped delay-line having equal length delays between the inputs of the CMOS line drivers. The signal will typically travel at a speed of less than 200 mm/ns in a buried stripline. The length of the delay line between each tap is approximately 112 mm. In the exemplary embodiment of the present invention, the tapped delay trace is a buried stripline on a 6 layer printed circuit board. The stripline runs in layer 4, and layer 2 and 6 are ground planes on each side of the stripline. The width of the stripline is approximately 0.2 mm, and spacing between each stripline is approximately 0.2 mm. This results in an impedance of approximately 75 ohms, and a delay of approximately 180 mm/ns. The resulting trapezoidal wave has a rise and fall time of approximately 12.5 ns.
The output of the twenty paralleled resistors is lowpass filtered with a 1200 pF capacitor, C3, to ground. The resulting output impedance of the power oscillator, at node 108, 110 is approximately (25+82)/20 ohm=5 ohm in parallel with 1200 pF, or approximately 3.3 ohm at 13.56 MHz. This is sufficiently low for driving a parallel tuned antenna through a capacitive network, without loading the Q factor of the tuned circuit excessively. As the impedance of the node 108, 110 is very low, the tuned circuit C1, L1 effectively has C2 connected in parallel to ground. C2 and C1 will typically have a value of 220 pF.
The point in time where each individual buffer switches is distributed over a period equal to the resulting rise time of the output wave form, resulting in a transient current draw from the power supply that is distributed in time as well. If for example, twenty (20) buffers are used, the resulting transient current draw can be twenty (20) times lower and spread over a twenty (20) times longer period, compared to a system where all buffers switch at the same time. This reduces the amplitude and bandwidth of the resulting emitted EMI from the circuit considerably.